Includes bibliographical references and index.

Emerging Nanoelectronic Devices; Contents; Preface; List of Contributors; Acronyms; Part One: Introduction; 1. The Nanoelectronics Roadmap; 1.1 Introduction; 1.2 Technology Scaling: Impact and Issues; 1.3 Technology Scaling: Scaling Limits of Charge-based Devices; 1.4 The International Technology Roadmap for Semiconductors; 1.5 ITRS Emerging Research Devices International Technology Working Group; 1.5.1 ERD Editorial Team; 1.5.2 Vision and Mission; 1.5.3 Scope; 1.6 Guiding Performance Criteria; 1.6.1 Nanoinformation Processing; 1.6.2 Nanoelectronic Device Taxonomy.

1.6.3 Fundamental Guiding Principles -- ``Beyond CMOS ́ ́ Information Processing1.6.4 Current Technology Requirements for CMOS Extension and Beyond CMOS Memory and Logic Technologies; 1.7 Selection of Nanodevices as Technology Entries; 1.8 Perspectives; References; 2. What Constitutes a Nanoswitch? A Perspective; 2.1 The Search for a Better Switch; 2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain; 2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain?; 2.3.1 Operation of an MTJ; 2.3.2 W-R Unit with Electrical Isolation; 2.3.3 Does This W-R Unit Have Gain?

2.4 Giant Spin Hall Effect: A Route to Gain2.4.1 Concatenability; 2.4.2 Proof of Gain and Directionality; 2.5 Other Possibilities for Switches with Gain; 2.5.1 All-spin Logic; 2.6 What do Alternative Switches Have to Offer?; 2.6.1 Energy-Delay Product; 2.6.2 Beyond Boolean Logic; 2.7 Perspective; 2.8 Summary; Acknowledgments; References; Part Two: Nanoelectronic Memories; 3. Memory Technologies: Status and Perspectives; 3.1 Introduction: Baseline Memory Technologies; 3.2 Essential Physics of Charge-based Memory; 3.3 Dynamic Random Access Memory.

3.3.1 Total Energy Required to Create/Maintain the Content of a Memory Cell3.3.2 DRAM Access Time (WRITE or READ); 3.3.3 Energy-Space-Time Compromise for DRAM; 3.4 Flash Memory; 3.4.1 Store; 3.4.2 Write; 3.4.3 Read; 3.4.4 Energetics of Flash Memory; 3.5 Static Random Access Memory; 3.5.1 SRAM Access Time; 3.5.2 SRAM Scaling; 3.6 Summary and Perspective; Appendix: Memory Array Interconnects; Acknowledgments; References; 4. Spin Transfer Torque Random Access Memory; 4.1 Chapter Overview; 4.2 Spin Transfer Torque; 4.2.1 Background of Spin Transfer Torque.

4.2.2 Experimental Observation of Spin Transfer Torque4.3 STT-RAM Operation; 4.3.1 Design of STT-RAM Cells; 4.3.2 Key Parameters for Operation; 4.4 STT-RAM with Perpendicular Anisotropy; 4.5 Stack and Material Engineering for Jc Reduction; 4.5.1 Dual Pinned Structure; 4.5.2 Nanocurrent Channel Structure Design; 4.5.3 Electric Field Assisted Switching; 4.6 Ultra-Fast Switching of MTJs; 4.7 Spin-Orbit Torques for Memory Application; 4.8 Current Demonstrations for STT-RAM; 4.9 Summary and Perspectives; References; 5. Phase Change Memory; 5.1 Introduction; 5.2 Device Operation.

Emerging Nanoelectronic Devices focuses on the future direction of semiconductor and emerging nanoscale device technology. As the dimensional scaling of CMOS approaches its limits, alternate information processing devices and microarchitectures are being explored to sustain increasing functionality at decreasing cost into the indefinite future. This is driving new paradigms of information processing enabled by innovative new devices, circuits, and architectures, necessary to support an increasingly interconnected world through a rapidly evolving internet. This original title provides a fresh.

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