000 04282cam a2200889Ka 4500
001 ocn729726229
003 OCoLC
005 20171119083024.0
006 m o d
007 cr cn|||||||||
008 110609s2011 enka ob 001 0 eng d
010 _z 2010045678
020 _a9781119995852
_q(electronic bk.)
020 _a111999585X
_q(electronic bk.)
020 _a9780470977927
_q(electronic bk.)
020 _a0470977922
_q(electronic bk.)
020 _z9780470688472
020 _z0470688475
020 _z9780470977972
020 _z0470977973
024 8 _a9786613373892
029 1 _aAU@
_b000047226132
029 1 _aAU@
_b000050060945
029 1 _aDEBBG
_bBV040900913
029 1 _aDEBSZ
_b372729940
029 1 _aDEBSZ
_b378279998
029 1 _aDEBSZ
_b381369420
029 1 _aDKDLA
_b820120-katalog:000556355
029 1 _aHEBIS
_b299832473
029 1 _aNZ1
_b13876206
029 1 _aDEBBG
_bBV043393202
035 _a(OCoLC)729726229
_z(OCoLC)704380182
_z(OCoLC)742947721
_z(OCoLC)765135622
_z(OCoLC)810071451
_z(OCoLC)839224154
_z(OCoLC)961512165
_z(OCoLC)962669173
037 _a10.1002/9781119995852
_bWiley InterScience
_nhttp://www3.interscience.wiley.com
040 _aDG1
_beng
_epn
_cDG1
_dBTCTA
_dOCLCQ
_dE7B
_dCOO
_dLGG
_dYDXCP
_dB24X7
_dCDX
_dOCLCQ
_dUMI
_dDEBSZ
_dOCLCO
_dOCLCQ
_dN$T
_dTVG
_dOCLCA
_dOCLCQ
_dRIV
_dOCLCQ
_dEBLCP
_dOCLCQ
_dOCLCF
_dOCLCQ
_dDEBBG
_dAZK
049 _aMAIN
050 4 _aTK7885.7
_b.R87 2011
072 7 _aCOM
_x036000
_2bisacsh
072 7 _aTEC
_x008030
_2bisacsh
072 7 _aTEC
_x008050
_2bisacsh
082 0 4 _a621.39/5
_222
100 1 _aRushton, Andrew,
_d1962-
245 1 0 _aVHDL for logic synthesis /
_cAndrew Rushton.
_h[electronic resource]
250 _a3rd ed.
260 _aChichester, West Sussex, U.K. :
_bWiley,
_c2011.
300 _a1 online resource (xvi, 466 pages) :
_billustrations
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
504 _aIncludes bibliographical references and index.
505 0 _aFront Matter -- Introduction -- Register-Transfer Level Design -- Combinational Logic -- Basic Types -- Operators -- Synthesis Types -- Std_Logic_Arith -- Sequential VHDL -- Registers -- Hierarchy -- Subprograms -- Special Structures -- Test Benches -- Libraries -- Case Study -- Appendix A: Package Listings -- Appendix B: Syntax Reference -- References -- Index.
520 _a"Macrocycles: Construction, Chemistry and Nanotechnology Applications is an essential introduction this important class of molecules and describes how to synthesise them, their chemistry, how they can be used as nanotechnology building blocks, and their applications"--
_cProvided by publisher.
588 0 _aPrint version record.
650 0 _aVHDL (Computer hardware description language)
650 0 _aLogic design
_xData processing.
650 0 _aComputer-aided design.
650 0 4 _aVHDL (Bilgisayar donanımı tanımlama dili)
650 0 4 _aMantık tasarımı
_xBilgi işlem.
650 0 4 _aBilgisayar destekli tasarım.
650 4 _aVHDL (Computer hardware description language)
650 4 _aLogic design
_xData processing.
650 4 _aComputer-aided design.
650 7 _aCOMPUTERS
_xComputer Engineering.
_2bisacsh
650 7 _aCOMPUTERS
_xLogic Design.
_2bisacsh
650 7 _aTECHNOLOGY & ENGINEERING
_xElectronics
_xCircuits
_xLogic.
_2bisacsh
650 7 _aTECHNOLOGY & ENGINEERING
_xElectronics
_xCircuits
_xVLSI & ULSI.
_2bisacsh
650 7 _aComputer-aided design.
_2fast
_0(OCoLC)fst00872701
650 7 _aLogic design
_xData processing.
_2fast
_0(OCoLC)fst01002048
650 7 _aVHDL (Computer hardware description language)
_2fast
_0(OCoLC)fst01163476
650 7 _aVHDL (Computer hardware description language)
_2local
650 7 _aLogic design / Data processing.
_2local
650 7 _aComputer-aided design.
_2local
655 4 _aElectronic books.
655 4 _aLlibres electrònics.
776 0 8 _iPrint version:
_aRushton, Andrew.
_tVHDL for logic synthesis.
_b3rd ed.
_dChichester, West Sussex, U.K. : Wiley, 2011
_z9780470688472
_w(DLC) 2010045678
_w(OCoLC)664324141
856 4 0 _uhttp://onlinelibrary.wiley.com/book/10.1002/9781119995852
_zWiley Online Library
942 _2ddc
_cBK
999 _c205104
_d205104