| 000 | 02632cam a2200601Ki 4500 | ||
|---|---|---|---|
| 001 | ocn870263361 | ||
| 003 | OCoLC | ||
| 005 | 20171031100058.0 | ||
| 006 | m o d | ||
| 007 | cr cnu|||unuuu | ||
| 008 | 140210s2014 enk ob 001 0 eng d | ||
| 020 |
_a9781118790137 _q(electronic bk.) |
||
| 020 |
_a1118790138 _q(electronic bk.) |
||
| 020 |
_a9781118790229 _q(electronic bk.) |
||
| 020 |
_a1118790227 _q(electronic bk.) |
||
| 020 | _a9781848215931 | ||
| 020 | _a1848215932 | ||
| 024 | 7 |
_a10.1002/9781118790229 _2doi |
|
| 029 | 1 |
_aCHNEW _b000694615 |
|
| 029 | 1 |
_aCHNEW _b000694619 |
|
| 029 | 1 |
_aNZ1 _b15495716 |
|
| 029 | 1 |
_aDEBBG _bBV043396544 |
|
| 029 | 1 |
_aCHVBK _b374456720 |
|
| 029 | 1 |
_aCHNEW _b000886753 |
|
| 035 |
_a(OCoLC)870263361 _z(OCoLC)961590770 _z(OCoLC)962707582 |
||
| 040 |
_aDG1 _beng _erda _epn _cDG1 _dYDXCP _dE7B _dUMC _dOCLCF _dOCLCQ _dCOO _dOCLCQ _dDEBBG |
||
| 049 | _aMAIN | ||
| 050 | 4 | _aQA76.54 | |
| 082 | 0 | 4 |
_a004.33 _223 |
| 100 | 1 |
_aRochange, Christine, _eauthor. |
|
| 245 | 1 | 0 |
_aTime-predictable architectures / _cChristine Rochange, Sascha Uhrig, Pascal Sainrat. _h[electronic resource] |
| 264 | 1 |
_aLondon, UK : _bISTE, Ltd. ; _aHoboken, NJ : _bJohn Wiley & Sons, Inc., _c2014. |
|
| 264 | 4 | _c©2014 | |
| 300 | _a1 online resource. | ||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
||
| 490 | 1 | _aFocus series | |
| 504 | _aIncludes bibliographical references and index. | ||
| 505 | 0 | _aReal-Time Systems and Time Predictability / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Timing Analysis of Real-Time Systems / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Current Processor Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Memory Hierarchy / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Multicores / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Example Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat. | |
| 588 | 0 | _aPrint version record. | |
| 650 | 0 | _aReal-time data processing. | |
| 650 | 0 | _aComputer architecture. | |
| 650 | 7 |
_aComputer architecture. _2fast _0(OCoLC)fst00872026 |
|
| 650 | 7 |
_aReal-time data processing. _2fast _0(OCoLC)fst01091219 |
|
| 655 | 4 | _aElectronic books. | |
| 700 | 1 |
_aUhrig, Sascha, _eauthor. |
|
| 700 | 1 |
_aSainrat, Pascal, _eauthor. |
|
| 776 | 0 | 8 |
_iPrint version: _aRochange, Christine, author. _tTime-predictable architectures _z9781848215931 _w(OCoLC)868374827 |
| 830 | 0 | _aFocus series. | |
| 856 | 4 | 0 |
_uhttp://onlinelibrary.wiley.com/book/10.1002/9781118790229 _zWiley Online Library |
| 942 |
_2ddc _cBK |
||
| 999 |
_c207272 _d207272 |
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