| 000 | 01289cam a2200337 i 4500 | ||
|---|---|---|---|
| 001 | 19918506 | ||
| 003 | BD-DhUL | ||
| 005 | 20191006125206.0 | ||
| 008 | 170818s2018 flu 001 0 eng | ||
| 010 | _a 2017022734 | ||
| 020 | _a9781138099951 (hardback : acidfree paper) | ||
| 040 |
_aDLC _beng _erda _cDLC _dDLC _dBD-DhUL |
||
| 042 | _apcc | ||
| 050 | 0 | 0 |
_aTK7868.D5 _bC3948 2018 |
| 082 | 0 | 0 |
_a621.381 _bCAV _223 |
| 100 | 1 |
_aCavanagh, Joseph, _eauthor. |
|
| 245 | 1 | 0 |
_aVerilog HDL design examples / _cJoseph Cavanagh. |
| 264 | 1 |
_aBoca Raton : _bCRC Press, Taylor & Francis Group, CRC Press is an imprint of the Taylor & Francis Group, an informa business, _c[2018] |
|
| 300 |
_axvii, 655 p. : _bill. ; _c26 cm |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_aunmediated _bn _2rdamedia |
||
| 338 |
_avolume _bnc _2rdacarrier |
||
| 365 |
_aGBP _b99.0 |
||
| 504 | _aIncludes index. | ||
| 650 | 0 |
_aDigital electronics _xComputer-aided design. |
|
| 650 | 0 | _aLogic design. | |
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 906 |
_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg |
||
| 942 |
_2ddc _cBK |
||
| 955 |
_bcf25 2017-08-18 _icf25 2017-08-18 to Dewey _axn08 2018-06-27 1 copy rec'd., to CIP ver. _ark20 2018-06-29 book received in ART _urk47 2018-09-14 rev. rk47 |
||
| 999 |
_c249994 _d249994 |
||