000 01322cam a2200313 a 4500
001 3924400
003 BD-DhUL
005 20150114141938.0
008 921014s1993 maua b 101 0 eng
010 _a 92035290
020 _a0792393082 (alk. paper)
040 _aDLC
_cDLC
_dDLC
_dBD-DhUL
050 0 0 _aTK7868.L6
_bL627 1993
082 0 0 _a621.395
_220
_bLOG
245 0 0 _aLogic synthesis and optimization /
_cedited by Tsutomu Sasao.
260 _aBoston :
_bKluwer Academic Publishers,
_cc1993.
300 _axv, 375 p. :
_bill. ;
_c25 cm.
365 _aUS$
_b247.00
440 4 _aThe Kluwer international series in engineering and computer science.
_pVLSI, computer architecture, and digital signal processing
504 _aIncludes bibliographical references and index.
650 0 _aLogic circuits
_xComputer-aided design.
650 0 _aLogic design
_xData processing.
700 1 _aSasao, Tsutomu,
_d1950-
856 4 2 _3Publisher description
_uhttp://www.loc.gov/catdir/enhancements/fy0820/92035290-d.html
856 4 1 _3Table of contents only
_uhttp://www.loc.gov/catdir/enhancements/fy0820/92035290-t.html
906 _a7
_bcbc
_corignew
_d1
_eocip
_f19
_gy-gencatlg
942 _2ddc
_cBK
955 _apc17 to ja00 10-14-92; jf05 10/14/92; jf08 10-15-92; jf13 10-15-92; aa07 10-16-92; CIP ver. pv06 01-29-93
999 _c30903
_d30903