000			01603cam a22003614a 4500
001			16558862
003			BD-DhUL
005			20150115155052.0
008			101201s2010 paua b 001 0 eng
010			_a 2010045850
020			_a9781609602123 (hardcover)
020			_a9781609602147 (ebook)
040			_aDLC _cDLC _dBD-DhUL _dBD-DhUL
042			_apcc
050	0	0	_aTK7895.E42 _bD467 2010
082	0	0	_a621.3815 _222 _bUBD
245	0	0	_aDesign and test technology for dependable systems-on-chip / _cRaimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
260			_aHershey, PA : _bInformation Science Reference, _cc2010.
300			_axxv, 550 p. : _bill. ; _c29 cm.
365			_aUS$ _b162.00
504			_aIncludes bibliographical references (p. 494-533) and index.
520			_a"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"-- _cProvided by publisher.
650		0	_aSystems on a chip _xDesign and construction.
650		0	_aNetworks on a chip. _xDesign and construction.
650		0	_aSystems on a chip _xTesting.
650		0	_aNetworks on a chip _xTesting.
700	1		_aUbar, Raimund, _d1941-
700	1		_aRaik, Jaan, _d1972-
700	1		_aVierhaus, Heinrich Theodor, _d1951-
906			_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg
942			_2ddc _cBK
955			_bxh12 2010-12-01 _ixh12 2010-12-01 _axe11 2011-05-18 2 copies rec'd., to CIP ver.
999			_c31781 _d31781