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020 _a9780852967782
020 _a0852967780
035 _a(OCoLC)ocm45351181
040 _aUKM
_beng
_cUKM
_dIXA
_dC#P
_dUNA
_dBAKER
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_dOCLCG
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042 _alccopycat
050 0 0 _aQC611.8.S5
_bS77 2001
082 0 4 _a621.38152
_221
082 0 4 _a620.193
_221
_bSTR
084 _aRL 624
_2blsrissc
084 _aELT 329f
_2stub
084 _aPHY 687f
_2stub
084 _aUP 3150
_2rvk
245 0 0 _aStrained silicon heterostructures :
_bmaterials and devices /
_cedited by C.K. Maiti, N.B. Chakrabarti and S.K. Ray.
260 _aLondon :
_bInstitution of Electrical Engineers,
_cc2001.
300 _axii, 496 p. :
_bill. ;
_c25 cm.
365 _aUS$
_b92.07
490 1 _aIEE circuits, devices and systems series
_v12
504 _aIncludes bibliographical references and index.
505 0 _aIntroduction -- Strained layer epitaxy -- Electronic properties of alloy layers -- Gate dielectrics on strained layers -- SiGe heterojunction bipolar transistors -- Heterostructure field effect transistors -- BICFET, RTD and other devices -- MODFETs -- Contact metallization on strained layers -- Si/SiGe optoelectronics.
650 0 _aHeterostructures.
650 0 _aSilicon.
650 7 _aHeterostructures.
_2fast
650 7 _aSilicon.
_2fast
650 0 7 _aHeterostruktur.
_2swd
650 0 7 _aSilicium.
_2swd
700 1 _aMaiti, C. K.
700 1 _aChakrabarti, N. B.
700 1 _aRay, S. K.,
_cDr.
710 2 _aInstitution of Electrical Engineers.
776 0 8 _iOnline version:
_tStrained silicon heterostructures.
_dLondon : Institution of Electrical Engineers, c2001
_w(OCoLC)606912463
830 0 _aIEE circuits, devices and systems series ;
_v12.
906 _a7
_bcbc
_ccopycat
_d2
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_f20
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942 _2ddc
_cBK
955 _brl09 2014-08-04 z-processor
_irl09 2014-08-29 ; to CALM
999 _c33065
_d33065