000 00634nam a22001817a 4500
003 BD-DhUL
005 20151029151904.0
008 151029s2007 BG a|||| m||| 00| 0 eng d
040 _aBD-DhUL
_cBD-DhUL
082 _a004
_bREA
245 _aRealization and optimization of reversible arithmetic logic unit /
_h[MS Thesis]
260 _aDhaka :
_bUniversity of Dhaka,
_c2007.
300 _avii, 54p. :
_bill ;
_c29 cm.
500 _aThesis (B.Sc.) - Department of Computer Science and engineering, Universitiy of Dhaka, 2003-04.
504 _aIncludes bibliographical references
650 0 0 _aComputer science
942 _2ddc
_cREF
999 _c42416
_d42416