000 | 00634nam a22001817a 4500 | ||
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003 | BD-DhUL | ||
005 | 20151029151904.0 | ||
008 | 151029s2007 BG a|||| m||| 00| 0 eng d | ||
040 |
_aBD-DhUL _cBD-DhUL |
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082 |
_a004 _bREA |
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245 |
_aRealization and optimization of reversible arithmetic logic unit / _h[MS Thesis] |
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260 |
_aDhaka : _bUniversity of Dhaka, _c2007. |
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300 |
_avii, 54p. : _bill ; _c29 cm. |
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500 | _aThesis (B.Sc.) - Department of Computer Science and engineering, Universitiy of Dhaka, 2003-04. | ||
504 | _aIncludes bibliographical references | ||
650 | 0 | 0 | _aComputer science |
942 |
_2ddc _cREF |
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999 |
_c42416 _d42416 |