| 000 | 00630nam a22001817a 4500 | ||
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| 003 | BD-DhUL | ||
| 005 | 20151101092008.0 | ||
| 008 | 151101s2008 BG a|||| m||| 00| 0 eng | | ||
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_aBD-DhUL _cBD-DhUL |
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| 082 |
_a621.395 _bREA |
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| 245 | 0 | 0 |
_aRealization of reversible ternary logic circuits / _h[MS Thesis] |
| 260 |
_aDhaka : _bUniversity of Dhaka, _c2008. |
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| 300 |
_avii, 53 p. : _b ill. ; _c29 cm. |
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| 500 | _aThesis (MS )--Department of Computer Science & Engineering, University of Dhaka, Session : 2004-2005. | ||
| 504 | _aIncludes bibliographical references. | ||
| 650 | 0 | _aElectric circuits | |
| 942 |
_2ddc _cREF |
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| 999 |
_c42428 _d42428 |
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